1. Technical Field
The present invention generally relates to a semiconductor memory device and a method of operating the same, and relates to a semiconductor memory device for storing data and a method of operating the same.
2. Related Art
Recently, a semiconductor memory device, specifically a flash memory device where data in a memory cell is maintained without being extinguished when power is not supplied has been continuously used as a data storage medium. However threshold voltage distribution of a programmed memory cell in the flash memory device may be changed by various causes while a program operation is performed, and thus malfunction of the flash memory device may occur.
FIG. 1 and FIG. 2 are views illustrating a program method when data of 2 bits is stored in one memory cell in conventional flash memory device. Particularly, FIG. 1 illustrates a method of programming a most significant bit MSB page after a least significant LSB page is programmed and a program state formed according to the programming. FIG. 2 illustrates a method of programming a block including plural pages. In FIG. 1, the horizontal axis represents a threshold voltage of a memory cell and the vertical axis represents the number of memory cells.
In FIG. 1, before a program operation is performed, the memory cells have an erase state E. In the case where a least significant bit LSB data is programmed (i.e., step (b)), the memory cells have two states, i.e. erase state E and least program state LP according to a threshold voltage (i.e., Vth) distribution. Memory cells having a threshold voltage corresponding to the erase state E may maintain the erase state E or have the least program state LP. The least program state LP means a state obtained by programming a least significant bit LSB of data of 2 bits. After the LSB data is programmed, the most significant bit MSB data is programmed (i.e. step (C)). Memory cells having a threshold voltage corresponding to an erase state E of the least significant bit LSB may maintain the erase state E or be programmed to a first program state P1 at a first programming voltage PV1. Memory cells having a threshold voltage corresponding to the least program state LP at a Least programming voltage LPV may be programmed to a second program state P2 at a second programming voltage PV2, or a third program state P3 at a third programming voltage PV3 when the most significant bit MSB is programmed.
In FIG. 2(a), a block includes a page, every LSB and MSB of one page may be programmed (i.e., PGM), and then a program operation may be performed for the next page. For example, a LSB program and a MSB program regarding a WL1 are performed, and then a LSB program and a MSB program regarding a WL2 are performed. That is,a LSB program and MSB program regarding a WLk is performed, and then a LSB program and MSB program regarding a WLk+1 is performed, where k is a positive integer, greater than or equal to 1 and less than or equal to n−1. In FIG. 2(b), after the LSB of one page is programmed, the MSB of the previous page is programmed immediately. For example, a LSB program regarding each of a WL1 and a WL2 is sequentially performed, and then a MSB program regarding the WL1 is performed. A LSB program regarding the WL3 is performed, and then a MSB program regarding the WL2. That is, a MSB program regarding a WLk is performed after a LSB program regarding a WLk+1 is performed, where k is a positive integer, greater than or equal to 1 and less than or equal to n−1. It is known that interference in a direction of a word according to the method in FIG. 2(b) is smaller than that according to the method in FIG. 2(a). However, the time it takes for programming becomes longer in the case where the conventional method in FIG. 1 and FIG. 2 is used, and the width of the threshold voltage formed according to the programming is comparatively great. In addition, threshold voltage of memory cell, about which a program operation is finished, shifts due to interference when the program operation is performed. This occurrence causes the malfunction of the semiconductor memory device.